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description the CXA3512R is a driver ic for the analog inputs of svga or higher sony polycrystalline silicon tft lcd panels. it has a line invert amplifier and analog demultiplexers, as well as the timing generator and output buffers required for these. the CXA3512R can directly drive an lcd panel. the vcom setting circuit and precharge pulse waveform generator are also on-chip. features high-speed signal processing supports xga high refresh signal overall wide band response low output deviation by on-chip output offset cancel circuit invert amplifier with small phase delay difference between inverted signal and non-inverted signal on-chip timing generator with ecl dot clock phase adjustment function vcom voltage generation circuit precharge pulse waveform generation circuit absolute maximum ratings supply voltage vcc 16 v v dd 5.5 v operating temperature ?0 to +70 ? storage temperature ?5 to +150 ? allowable power dissipation p d 2300 mw (single layered board mounted) recommended operating conditions supply voltage vcc 15.0 to 15.5 v v dd 4.75 to 5.25 v ambient temperature ?0 to +70 ? lcd driver ?1 e99803a9z-ps sony reserves the right to change products and specifications without prior notice. this information does not convey any licens e by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustr ating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. CXA3512R 64 pin lqfp (plastic)
? 2 CXA3512R block diagram s / h s / h s / h v c o m o f f s e t c a n c e l b u f f e r s / h s / h s / h o f f s e t c a n c e l b u f f e r s / h s / h s / h o f f s e t c a n c e l b u f f e r s / h s / h s / h o f f s e t c a n c e l b u f f e r s / h s / h s / h o f f s e t c a n c e l b u f f e r s / h s / h s / h o f f s e t c a n c e l b u f f e r 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 6 0 6 1 6 2 6 3 6 4 c a l _ r c a l _ o c a l _ i v d d d g n d m c l k m c l k x g n d g n d d l y c t r c l k o u t c l k o u t x n c c l k i n c l k i n x f / h _ c n t p r g p o l p r g n c n c p o s c t r 1 p o s c t r 2 n c g n d g n d s t a t u s e n b d 1 o r 2 d i r c t r n c n c d c f b s w n c v i d e o _ i v i d e o _ r v i d e o _ o s h _ i n n c v c c g n d g n d s i d _ i n s i d _ r s i d _ o f r p s i g c n t v c o m o f f v c o m o u t s h o u t 1 n c s h o u t 2 n c s h o u t 3 n c p v c c g n d g n d p g n d n c s h o u t 4 n c s h o u t 5 n c s h o u t 6 d c l o c k d e l a y s / h p u l s e s t i m i n g g e n e r a - t o r o f f s e t c a n c e l m o d e t i m i n g s i d i n v e r t a m p c a l i b r a - t i o n a m p
? 3 CXA3512R pin description pin no. symbol i/o standard voltage level equivalent circuit description 1 prgpol i high: 3 2.5v low: 0.8v open high selects the latch polarity of the prg pulse used as the time reference. high: prg pulse is latched at the falling edge of clkin. low: prg pulse is latched at the rising edge of clkin. select the polarity with sufficient timing margin after adjusting the analog video and clkin phases with dlyctr. 1 v d d 4 0 k 1 0 0 k 2 0 k 1 2 2 0 k v d d v d d v d d 2 prg i high: 3 2.5v low: 0.8v prg pulse input. see the timing chart. 2 v d d v d d 1 4 5 5 0 k 1 5 0 k v d d 5 0 k 5 6 posctr1 posctr2 i see table a-1. output phase adjustment. each pin has 4 setting values, for a total of 16 settings. (adjustment in 1 dot clock units in xga mode, 1/2 dot clock units in svga mode, and 1 dot clock units in sxga mode.) see tables a-1, a-2 and a-3. 5 6 v d d 6 0 k 2 k v d d 10 status i high: 3 2.5v low: 0.8v open high used in xga and uxga modes (when using 2 ics for a gamma- corrected ic). during forward scan, high: 2nd device, low: 1st device during reverse scan, high: 1st device, low: 2nd device see table b. 1 0 v d d 4 0 k 1 0 0 k 2 0 k 1 2 2 0 k v d d v d d v d d 11 enb i high: 3 2.5v low: 0.8v enb pulse input. see the timing chart. 1 1 v d d v d d 1 4 5 5 0 k 1 5 0 k v d d 5 0 k 13 d1or2 i high: 3 2.5v low: 0.8v open high clkout pin frequency selection. high: same frequency as mclk low: double the mclk frequency 1 3 v d d 4 0 k 1 0 0 k 2 0 k 1 2 2 0 k v d d v d d v d d
? 4 CXA3512R 14 dirctr i high: 3 2.5v low: 0.8v open high scan direction setting. low: output as a time series in descending order (reverse scan) of output pin symbol (in order from shout6 to shout1) high: output in ascending order (forward scan) 1 4 v d d 4 0 k 1 0 0 k 2 0 k 1 2 2 0 k v d d v d d v d d 16 dcfbsw i open high offset cancel circuit on/off switch. high: cancel circuit on use this pin at on (open). 1 6 v d d 4 0 k 1 0 0 k 1 0 v d d v d d 4 0 k 17 19 21 28 30 32 shout6 shout5 shout4 shout3 shout2 shout1 o 1.5 to 13.5v demultiplexer outputs. can be connected directly to the lcd input pins. 3 0 3 2 2 8 1 9 2 1 1 7 v c c v c c v c c 3 0 0 3 0 0 33 vcomout o 3 to 7v lcd common voltage of panel output. can be set to v sigcnt to (v sigcnt ?3v) by the pin 34 input. 7 0 v c c 3 3 v c c 1 4 5 6 0 k 5 0 0 v c c 5 0 0 34 vcomoff i 0 to 10v vcomout (pin 33) voltage setting. vcomout is the same potential as sigcnt for input of 0v, and approximately 3v lower than that for input of 10v. 3 4 v c c 2 k 1 0 0 k 6 0 v c c 35 sigcnt i 7v signal center voltage (inversion folded voltage) input. normally, set to 7v. 3 5 v c c 2 k 2 0 pin no. symbol i/o standard voltage level equivalent circuit description
? 5 CXA3512R 36 frp i high: 3 2.5v low: 0.8v invert pulse input. high: inverse low: non-inverse see the timing chart. 3 6 v d d v d d 1 0 k 1 0 0 k 5 0 v d d 37 sid_o o 2 to 12v sid block output. provide an external buffer for precharge. 3 7 v c c 1 4 5 7 8 k 0 . 2 p v c c 7 8 k 0 . 2 p 38 sid_r i 3.3v precharge signal invert offset adjustment. when using the cxa2111r sid, connect to the v33 output of the cxa2111r. 3 8 v c c 3 0 k v c c 1 0 39 sid_in i 2.3 to 3.3v precharge waveform input. can be connected directly to the cxa2111r sid output. connect to 5v when not using the sid block. 3 9 v c c 1 4 5 v c c 4 0 44 sh_in i 2 to 10v analog demultiplexer input. connect to the video_o (pin 45) output. do not input 2v or less. 4 4 v c c 2 0 0 5 5 0 2 0 0 45 video_o o 2 to 10v invert amplifier output. connect directly to pin 44. when using two CXA3512R in parallel in xga or uxga mode, use the invert amplifier of only one ic, and connect the output to pin 44 of both ics. 6 0 0 4 5 v c c v c c v c c v c c 6 0 0 pin no. symbol i/o standard voltage level equivalent circuit description
? 6 CXA3512R 46 video_r i 3.3v input the 100% white level dc of the signal input to video_i. when using the cxa2111r, connect to the v33 output of the cxa2111r. when using bipolar dac output for video_i, connect to the dac supply voltage. 4 6 v c c 3 0 k v c c 1 0 47 video_i i 2 to 3.3v video input. connect a gamma-corrected 1.5vp-p analog video output. can be connected directly to the cxa2111r video output. connect to 5v when not using the invert amplifier. 4 7 v c c 1 4 5 v c c 4 2 0 49 cal_r i 2.7v calibration level input for offset cancel. input the dc level during non- inverse with the most highly visible gradation. normally, approximately 2.5 to 3v. 4 9 v c c 1 4 5 v c c 5 0 50 cal_o o 3 to 11v calibration amplifier output. connect directly to pin 51. when using two CXA3512R in parallel in xga or uxga mode, use the calibration amplifier of only one ic, and connect the output to pin 51 of both ics. 5 0 v c c v c c 1 4 5 7 0 0 1 0 0 v c c 51 cal_i i 3 to 11v calibration level input for offset cancel. connect to cal_o. 5 1 v c c 3 0 k 3 0 k 54 55 mclk mclkx i pecl differential (amplitude 0.4v or more between v dd and 2v) or ttl input dot clock inputs. pecl differential input or ttl input. for ttl input, input to mclk and connect mclkx to gnd via a capacitor. always input the dot clock or equivalent signal to these pins even when not using clkout. (otherwise, noise may result.) 5 4 5 5 v d d 1 k 1 4 0 k 1 0 0 v d d 6 0 k pin no. symbol i/o standard voltage level equivalent circuit description
? 7 CXA3512R 58 dlyctr i 3 to 5v dot clock phase adjustment. the clkout phase relative to mclk can be changed by the voltage of this pin. connection to the cxa2111r dly_cnt output allows digital control using the i 2 c register of the cxa2111r. 5 8 v d d 1 0 k 2 5 v d d 59 60 clkout clkoutx o v dd ?0.3v to v dd phase-adjusted dot clock outputs. 5 9 6 0 v d d 1 5 0 v d d 1 m 1 m 62 63 clkin clkinx i v dd ?0.3v to v dd dot clock inputs for timing generation. connect the clkout (clkoutx) pin. when not using the clk phase adjustment function, the dot clock can also be input directly to these pins by pecl differential input. 6 2 6 3 v d d 1 4 5 2 k 1 0 0 2 k v d d v d d 64 f/h_cnt i high: 3 2.5v low: 0.8v open high shout output timing selection. high: shout 1 to 3 and shout 4 to 6 are output at different timing. low: shout 1 to 6 are output at the same timing. 6 4 v d d 4 0 k 2 0 k 1 2 2 0 k v d d 1 0 0 k v d d v d d 23 26 42 52 53 pgnd pv cc v cc v dd dgnd gnd 15.5v 15.5v 5v gnd power gnd. power v cc . connect directly to v cc . 15v power supply. 5v power supply. digital gnd. 8, 9, 24, 25, 40, 41, 56, 57 gnd gnd analog gnd. 3, 4, 7, 12, 15, 18, 20, 22, 27, 29, 31, 43, 48, 61 nc no connection. not connected to anything. pin no. symbol i/o standard voltage level equivalent circuit description
? 8 CXA3512R electrical characteristics (see electrical characteristics measurement circuit) (v dd = 5v, v cc = 15.5v, v sigcen = 7v, ta = 25 3 c) no. item symbol measurement contents min. typ. max. unit 1 2 3 4 5 6 7 8 9 10 11 12 v dd current consumption v cc current consumption input ?output gain invert amplifier gain invert amplifier slew rate invert amplifier output band width output delay deviation for inverse/non- inverse sid output gain sid block output slew rate vcom adjustable range first stage sh_out slew rate sh_out slew rate i dd i cc a shout a inv sr inv bw inv t diff a sid sr sid v com sr sh1 sr out i dd = i vdd i cc = i vcc1 + i vcc2 a shout = v shout (ac)/v in a inv = v inv (ac)/v in input a square wave from v in so that the v inv output amplitude is 3.0vp-p. measure the slew rate at 10 to 90% of output waveform rise or fall. (for inverse or non- inverse) input 2.5v dc, 100mvp-p ac from pin 47 (video_in) and measure v inv . the frequency that is ?db to 100khz. (for inverse or non-inverse) invert amplifier delay time difference for inverse and non- inverse. a sid = v sid (ac)/v sid_in input an invert pulse to pin 44 (frp), load capacitance c7 = 47pf, and apply dc input voltage to v sid_in so that v sid is 2.5v/11.5v. measure the slew rate at 10 to 90% of output waveform rise or fall. vcom output voltage when pin 34 (vcomoff) is varied from 0 to 10v. first stage sample-and-hold slew rate on block diagram. input a square wave from v in so that the v out1 to v out6 output amplitude is 3.5vp-p. measure the slew rate at 10 to 90% of output waveform rise or fall. (load 270pf, for inverse or non-inverse) 20 30 30 vsig ?2 28 45 3 2 700 90 2 4 50 700 150 42 65 4 4.4 vsig ma ma times times v/ s mhz ns times v/ s v v/ s v/ s measurement points i vdd i vcc1 i vcc2 v shout v in v inv v in v inv v inv v inv v sid v sid_in v sid v com v out1 to v out6
? 9 CXA3512R 13 14 15 16 17 18 19 20 21 22 mclk input frequency range tg operating frequency range video_i input signal range video_i input signal amplitude range shout minimum output voltage shout maximum output voltage output deviation between channels 1 output deviation between channels 2 output deviation between ics 1 output deviation between ics 2 f mclk f tg v inr v in v min v max d out1 d out2 d ic1 d ic2 d1or2 = high (clkout = mclk) maximum frequency at which the sample-and-hold timing pulse is output properly. video_i input voltage range when video_r is set to 3.3v. maximum signal amplitude range of video_i input signal minimum voltage at which sample-and-hold output (shout 1 to shout 6) can be output. maximum voltage at which sample-and-hold output (shout 1 to shout 6) can be output. value obtained by subtracting minimum v out1 to v out6 value from maximum v out1 to v out6 value when cal_r = 2.6v and video_i = 2.6v. value obtained by subtracting minimum v out1 to v out6 value from maximum v out1 to v out6 value when cal_r = 2.6v and video_i = 3.3v or 1.9v. value obtained by subtracting minimum v out1 to v out6 value from maximum v out1 to v out6 value when cal_r = 2.6v and video_i = 2.6v. (when using two CXA3512R) value obtained by subtracting minimum v out1 to v out6 value from maximum v out1 to v out6 value when cal_r = 2.6v and video_i = 3.3v or 1.9v. (when using two CXA3512R) 14 1.5 1.5 2 13 4 4 10 10 65 120 3.7 1.5 13.5 10 40 20 60 mhz mhz v v v v mvp-p mvp-p mvp-p mvp-p v out1 to v out6 v out1 to v out6 v out1 to v out6 v out1 to v out6 v out1 to v out6 v out1 to v out6 unless otherwise specified, pin setting conditions are as follows. (46) video_r = 3.3v, (47) video_i = 2.0v, (39) sid_in = 2.3v, (38) sid_r = 3.3v, (35) sigcnt = 7.0v, (34) vcomoff = 0v, (1) prgpol = 0v, (5) posctr1 = 0v, (6) posctr2 = 0v, (10) status = 0v, (13) d1or2 = 5v, (14) dirctr = 5v, (49) cal_r = 2.6v, (58) dlyctr = 4.0v, (64) f/h_cnt = 0v, (36) frp = 0v, f clk 32.5mhz no. item symbol measurement contents min. typ. max. unit measurement points
? 10 CXA3512R electrical characteristics measurement circuit v d d s w 2 v d d s w 3 v d d s w 4 v c c v d d d i f f b u f f e r 2 f r e q u e n c y f c l k 2 . 0 v v i n s / h s / h s / h v c o m o f f s e t c a n c e l b u f f e r s / h s / h s / h o f f s e t c a n c e l b u f f e r s / h s / h s / h o f f s e t c a n c e l b u f f e r s / h s / h s / h o f f s e t c a n c e l b u f f e r s / h s / h s / h o f f s e t c a n c e l b u f f e r s / h s / h s / h o f f s e t c a n c e l b u f f e r d c l o c k d e l a y s / h p u l s e s t i m i n g g e n e r a - t o r o f f s e t c a n c e l m o d e t i m i n g s i d i n v e r t a m p c a l i b r a - t i o n a m p 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 6 0 6 1 6 2 6 3 6 4 c a l _ r c a l _ o c a l _ i v d d d g n d m c l k m c l k x g n d g n d d l y c t r c l k o u t c l k o u t x n c c l k i n c l k i n x p r g p o l p r g n c n c p o s c t r 1 p o s c t r 2 n c g n d g n d s t a t u s e n b d 1 o r 2 d i r c t r n c n c d c f b s w n c v i d e o _ i v i d e o _ r v i d e o _ o s h _ i n n c v c c g n d g n d s i d _ i n s i d _ r s i d _ o f r p s i g c n t v c o m o f f v c o m o u t s h o u t 1 n c s h o u t 2 n c s h o u t 3 n c p v c c g n d g n d p g n d n c s h o u t 4 n c s h o u t 5 n c s h o u t 6 f / h _ c n t v 1 5 . 5 v 2 . 3 v v d d v d d v c c i v c c 1 v c o m v s i d _ i n v i n v v s i d c 1 2 7 0 p f v o u t 1 c 2 2 7 0 p f v o u t 2 c 3 2 7 0 p f v o u t 3 c 4 2 7 0 p f v o u t 4 c 5 2 7 0 p f v o u t 5 c 6 2 7 0 p f v o u t 6 a i v d d a v c c i v c c 2 a s w 1 5 v
? 11 CXA3512R level diagram video_i to shout (sigcnt = 7v, video_r = input 100% white level) 3 . 3 3 3 v 1 0 . 6 6 7 v v c c s i g c n t = 7 v v i d e o _ i = 1 . 5 v p - p v w h i t e v b l a c k g n d v i d e o _ i 2 . 0 t i m e s v i d e o _ o s h _ i n s h o u t 1 . 5 t i m e s 6 . 3 3 3 v 7 . 6 6 7 v 1 2 . 5 v 8 v 6 v 1 . 5 v video_i to video_o the formulas for calculating the video_i to shout internal dc gain are as follows. for non-inverse: video_o = 2.0 (video_i ?video_r) + sigcnt (1 1/10.5) shout = 3.0 (video_i ?video_r) + sigcnt (1 1/7) for inverse: video_o = ?.0 (video_i ?video_r) + sigcnt (1 + 1/10.5) shout = ?.0 (video_i ?video_r) + sigcnt (1 + 1/7)
? 12 CXA3512R description of operation 1. invert amplifier block v i d e o _ r v i d e o _ o v i d e o _ i f r p v i n a p p r o x . 3 v i n a p p r o x . 1 v v s i g c n t i n p u t l e v e l ( 1 0 0 % w h i t e ) c a l i b r a t i o n l e v e l the CXA3512R is designed so that the optimal signal for the lcd panel is output from the shout pins when a signal in the range from 1.8 to 3.3v is applied to the video_i input. as shown in the figure above, when a g corrected video signal is input to video_i, the signal is inverse/non-inverse amplified according to the frp input (ttl level) and output from video_o. the dc level is determined by the video_r input. input a level equivalent to 100% white of input. also, when not using the invert amplifier, connect video_i to 5v. 2. analog demultiplexer block the sh_in analog input signal is converted from a time series signal to a 6-channel (or 12-channel) cyclic parallel signal by the sample-and-hold group which is appropriately controlled by the on-chip timing generator. these signals pass through a fixed-gain (= 1.5 times) buffer amplifier and are output to shout. these outputs can directly drive the input load of the lcd panel. when using a svga panel, connect the (6-channel output) video_o output directly to the adjacent sh_in. xga panels use 12-channel output, so short the sh_in of two CXA3512R and connect them to the video_o output of one of the ic. the on-chip tg recognizes master/slave by the low/high status (pin 10) input. for forward scan, the output alternates between the ics in the order of master shout1 ? slave shout1 ? master shout2 ? slave shout2 ? master shout3 and so on. connect the wiring to the lcd panel inputs in this order. the sample-and-hold pulse generation timing is shown on the following pages. these pulses are not output and are used only inside the ic.
? 13 CXA3512R internal sample-and-hold pulse timing chart 1 forward scan (dirctr = high), f/h_cnt = high s h 1 _ 1 c h s h 1 _ 6 c h s h 1 _ 2 c h s h 1 _ 5 c h s h 1 _ 3 c h s h 1 _ 4 c h s h 1 _ 4 c h s h 1 _ 3 c h s h 1 _ 5 c h s h 1 _ 2 c h s h 1 _ 6 c h s h 3 _ 4 t o 6 s h 1 _ 1 c h s h 2 _ 1 t o 3 s h 2 _ 4 t o 6 s h 2 _ 4 t o 6 s h 2 _ 1 t o 3 s h 3 _ 1 t o 3 s h 3 _ 4 t o 6 s l a v e ( s t a t u s = h i g h ) m a s t e r ( s t a t u s = l o w ) w h e n f / h _ c n t = l o w : s a m e t i m i n g a s s h 3 _ 1 t o 3 w h e n f / h _ c n t = l o w : s a m e t i m i n g a s s h 3 _ 1 t o 3 s h 3 _ 1 t o 3
? 14 CXA3512R internal sample-and-hold pulse timing chart 2 reverse scan (dirctr = low), f/h_cnt = high s h 1 _ 1 c h s h 1 _ 6 c h s h 1 _ 2 c h s h 1 _ 5 c h s h 1 _ 3 c h s h 1 _ 4 c h s h 1 _ 4 c h s h 1 _ 3 c h s h 1 _ 5 c h s h 1 _ 2 c h s h 1 _ 6 c h s h 3 _ 4 t o 6 s h 1 _ 1 c h s h 2 _ 1 t o 3 s h 2 _ 4 t o 6 s h 2 _ 4 t o 6 s h 2 _ 1 t o 3 s h 3 _ 1 t o 3 s h 3 _ 4 t o 6 s l a v e ( s t a t u s = h i g h ) m a s t e r ( s t a t u s = l o w ) w h e n f / h _ c n t = l o w : s a m e t i m i n g a s s h 3 _ 4 t o 6 w h e n f / h _ c n t = l o w : s a m e t i m i n g a s s h 3 _ 4 t o 6 s h 3 _ 1 t o 3
? 15 CXA3512R 3. timing generator (tg) block the on-chip tg operates by one pair of differential clock inputs (clk_in, clk_inx) and two horizontal sync signal inputs (prg, enb), and generates the timing pulses needed by the demultiplexer block and the output deviation cancel circuit. the various operation modes can be designated by the pin voltage settings. input timing signal conditions 3 0 c l k o r m o r e 6 0 c l k o r m o r e 4 c l k o r m o r e e n b p r g f r p 0 t o 5 c l k maintain the enb, prg and frp phase relationship shown in the timing chart above, with the clk_in input sync as 1 clk. in particular, when frp changes between high and low, be sure to input enb and prg as shown above. otherwise, the ic may suffer irrecoverable deterioration in the worst case. operation mode setting table b. * 1 the output phase can be shifted by 1/2-dot clock in svga/sxga mode by changing status. status d1or2 h/l * 1 l svga (6-channel mode) sxga (12-channel mode) l h xga/uxga (12-channel/24-channel mode) h h slave master scan direction setting the output scan direction can be changed by the dirctr (pin 14) input. pin 14 h l direction forward reverse scan order shout1 ? shout2 ? shout3 ? shout4 ? shout5 ? shout6 ? shout1 ? shout6 ? shout5 ? shout4 ? shout3 ? shout2 ? shout1 ? shout6 ? the scan direction can be changed by the pin 14 setting without changing other connections even when using two CXA3512R such as in xga mode.
? 16 CXA3512R output phase setting the phase of each shout output relative to the analog input can be adjusted in clk_in clock units by the pins 5 and 6 input levels. each input pin has 4 setting values, for a total of 16 settings. posctr1 is the lower bits setting, posctr2 is the upper bits setting, and the setting values are as shown in table a-1. setting value threshold 0 1 2 3 to 0.75v 1.15 to 1.50v 1.70 to 2.55v 2.95v to table a-1. setting voltage range for output phase setting value a 0 1 2 3 l hi-z hi-z h b l l h h table a-2. cmos logic connection setting value and cmos output pins there are two ways to use these pins. a. connect directly to the cxa2111r connect to the corresponding cxa2111r pins pos_cnt1 and pos_cnt2. this allows bit setting via the cxa2111r i 2 c bus. b. connect to cmos logic connect cmos logic as shown in the figure. this allows digital control by tri-state control of pin a. see table a-2. r1 is a threshold setting resistor that provides the voltage for setting values 1 and 2. the appropriate resistance value changes depending on the number of CXA3512R driven by one cmos logic (1-channel or 3- channel rgb drive, or one CXA3512R (6-outputs/ch) or two CXA3512R (12-outputs/ch)). recommended resistance values are given in table a-3. cmos logic connection CXA3512R usage and threshold setting resistor r1 5 b a c m o s c x a 3 5 1 2 r r 1 p o s _ c n t 1 o r p o s _ c n t 2 ( p i n 6 ) table a-3. r1 value 250k 150k rgb 1-channel drive rgb 3-channel drive 100k 47k 12 outputs 6 outputs 6 outputs 12 outputs cmos supply voltage = 3.3 to 5v
? 17 CXA3512R 4. dot clock phase adjustment block the CXA3512R has a function for adjusting the phase between the analog video input and the dot clock input to achieve stable reproduction of high definition images. images with no jitter and flicker can be reproduced by optimizing the setting. the 1/2-dot clock input to mclk and mclkx (pecl level) is input to the phase comparator of the on-chip pll clock generator. the output from clkout and clkoutx becomes the internal vco output. clkout is the same frequency as mclk when the d10r2 (pin 13) input is high, and twice the mclk frequency when the d10r2 input is low. a large amplitude logic with a threshold value of 1.5v can also be connected directly to mclk instead of pecl. in this case, connect mclkx to gnd via a capacitor of approximately 100pf. (pecl level input is recommended when the mclk input is used around 50mhz.) the clkout phase can be adjusted up to 180 according to the dc level (3 to 5v) of the dlyctr (pin 58) input. by connecting clkout to the tg clock input, the analog video signal and first stage sample-and-hold phases can be finely adjusted using the dlyctr dc level. when using two CXA3512R in xga mode, input the clkout of one CXA3512R to the clkin of both in order to match the timing of both ics. in this case, input the same clock to mlck of both ics. 5. calibration amplifier block the CXA3512R generates the deviation cancel circuit reference with a calibration amplifier in order to minimize the deviation between channels at the highest visibility level. input dc level equivalent to approximately 50% gray at video_i to cal_r (pin 49). in addition, directly connect the cal_o (pin 50) output to the adjacent cal_i. when using two CXA3512R in xga mode, connect the cal_o of one ic to the cal_i of both ics, and connect the unused cal_r to 5v. 6. sid block this block generates the precharge signal used by the lcd panel. the signal input to sid_in (pin 39) is folded at the sigcnt potential by frp in the same manner as the invert amplifier, and output to sid_o (pin 37). the gain is designed at approximately 4 times. the dc level is determined by sid_r, and is normally approximately 3.3v. sid_o cannot directly drive the precharge signal input of the lcd panel. therefore, connect sid_o via a buffer having sufficient current supply capability. sid_o dc calculation formula pin 36: low = non-inverse sid_o = 4 (sid_in ?sid_r) + 6/7 (sigcnt) pin 36: high = inverse sid_o = 4 (sid_r ?sid_in) + 8/7 (sigcnt) 7. vcom block this block sets the dc potential of the vcom level. the vcomoff (pin 34) potential sets the deviation relative to the sigcnt potential as follows. vcomoff = 0v: vcomout = sigcnt vcomoff = 10v: vcomout = sigcnt ?3v
? 18 CXA3512R combination with the cxa2111r used together with the cxa2111r, the CXA3512R can achieve most of the analog signal processing ( g correction, precharge waveform generation) required by lcd panels. in addition, i 2 c serial control of the following functions is possible using the i 2 c-controlled registers built into the cxa2111r. output phase adjustment (posctr1, 2) clock phase adjustment (dlyctr) scan direction (dirctr) connect the pins as shown in the table below to use the various functions. for details, see the cxa2111r specifications. cxa2111r CXA3512R rout (18), gout (16) or bout (14) sidout (6) pos_cnt (1) pos_cnt (2) dlk_cnt (3) dir_cnt (4) v33 (8) video signal precharge waveform output phase clock phase scan direction reference level vide_in (47) sid_in (39) posctr1 (5) posctr2 (6) dlyctr (58) dirctr (14) video_r (46) sid_r (38)
? 19 CXA3512R notes on operation 1. notes on mounting the CXA3512R consumes power of approximately 1w. be sure to take the following measures to prevent the ic temperature from rising. a. pins 8, 9, 24, 25, 40, 41, 56 and 57 (total 8 pins) are connected directly to the "die pad". electrically and thermally connect these pins to the inner layer gnd plane of a 4-layer substrate using multiple via. b. do not mount in high density on a small substrate. mounting to a 4-layer substrate with an inner layer copper foil thickness of 30 m or more is recommended. c. do not locate the CXA3512R downwind of high thermal loads (lamp, etc.) in sets with fans. do not locate the CXA3512R in portions with stagnant air flows in sets without fans. the wiring for the CXA3512R alone does not require special consideration, the skew with the prg pulse rise timing may cause problems when using a high-speed dot clock. particularly when using multiple CXA3512R, the timing of the prg used as the time reference inside the ic must be matched at the ic input pins. care should be taken when designing the board for the effects of propagation time and reflection, with the prg line also considered an analog line like mclk. if skew with the prg pulse poses a problem after adjusting the phase relationship between the analog video input and clk_in, it may be possible to solve this problem by adjusting the prgpol (pin 1) h/l setting for each ic. 2. input signals be sure to maintain the frp, enb and prg timings noted in "description of operation 3. timing generator (tg) block". special care should be taken to avoid frp transition without enb and prg. there is no particular problem when connecting the video_o output to sh_in, but in this case do not input voltages of 2v or less, or (v dd ?2v) or more.
? 20 CXA3512R application circuit 1 (to svga panel) v d d v c c s / h s / h s / h v c o m o f f s e t c a n c e l b u f f e r s / h s / h s / h o f f s e t c a n c e l b u f f e r s / h s / h s / h o f f s e t c a n c e l b u f f e r s / h s / h s / h o f f s e t c a n c e l b u f f e r s / h s / h s / h o f f s e t c a n c e l b u f f e r s / h s / h s / h o f f s e t c a n c e l b u f f e r d c l o c k d e l a y s / h p u l s e s t i m i n g g e n e r a - t o r o f f s e t c a n c e l m o d e t i m i n g s i d i n v e r t a m p c a l i b r a - t i o n a m p 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 6 0 6 1 6 2 6 3 6 4 c a l _ r c a l _ o c a l _ i v d d d g n d m c l k m c l k x g n d g n d d l y c t r c l k o u t c l k o u t x n c c l k i n c l k i n x f / h _ c n t p r g p o l p r g n c n c p o s c t r 1 p o s c t r 2 n c g n d g n d s t a t u s e n b d 1 o r 2 d i r c t r n c n c d c f b s w n c v i d e o _ i v i d e o _ r v i d e o _ o s h _ i n n c v c c g n d g n d s i d _ i n s i d _ r s i d _ o f r p s i g c n t v c o m o f f v c o m o u t s h o u t 1 n c s h o u t 2 n c s h o u t 3 n c p v c c g n d g n d p g n d n c s h o u t 4 n c s h o u t 5 n c s h o u t 6 2 0 k b u f f e r 0 . 1 0 . 1 v c c 1 0 k 5 . 1 k 5 . 1 k 5 v v c c 2 0 k v d d v d d 0 . 1 0 . 1 v c c 0 . 1 p s i g l c d p a n e l 1 0 1 5 . 5 v 0 . 1 1 0 1 c o m 2 4 s i g 1 7 s i g 2 5 s i g 3 3 s i g 4 2 s i g 5 4 s i g 6 6 s i d _ o u t c x a 2 1 1 1 r 6 v 3 3 8 r _ o u t 1 8 c l k h c x a 3 1 0 6 q 3 2 c l k l 3 1 g _ o u t 1 6 f r p n r g e n b b _ o u t 1 4 d l y _ c n t 3 p o s _ c t r 1 1 p o s _ c t r 2 2 d i r _ c n t 4 o p e n o p e n 1 0 0 . 1 ( l c x 0 2 6 ) application circuits shown are typical examples illustrating the operation of the devices. sony cannot assume responsibility fo r any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same .
? 21 CXA3512R application circuit 2 (to xga panel) s / h s / h s / h v c o m o f f s e t c a n c e l b u f f e r s / h s / h s / h o f f s e t c a n c e l b u f f e r s / h s / h s / h o f f s e t c a n c e l b u f f e r s / h s / h s / h o f f s e t c a n c e l b u f f e r s / h s / h s / h o f f s e t c a n c e l b u f f e r s / h s / h s / h o f f s e t c a n c e l b u f f e r d c l o c k d e l a y s / h p u l s e s t i m i n g g e n e r a - t o r o f f s e t c a n c e l m o d e t i m i n g s i d i n v e r t a m p c a l i b r a - t i o n a m p 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 6 0 6 1 6 2 6 3 6 4 c a l _ r c a l _ o c a l _ i v d d d g n d m c l k m c l k x g n d g n d d l y c t r c l k o u t c l k o u t x n c c l k i n c l k i n x f / h _ c n t p r g p o l p r g n c n c p o s c t r 1 p o s c t r 2 n c g n d g n d s t a t u s e n b d 1 o r 2 d i r c t r n c n c d c f b s w n c v i d e o _ i v i d e o _ r v i d e o _ o s h _ i n n c v c c g n d g n d s i d _ i n s i d _ r s i d _ o f r p s i g c n t v c o m o f f v c o m o u t s h o u t 1 n c s h o u t 2 n c s h o u t 3 n c p v c c g n d g n d p g n d n c s h o u t 4 n c s h o u t 5 n c s h o u t 6 2 0 k b u f f e r 0 . 1 0 . 1 v c c v d d v d d 1 0 k 5 . 1 k 5 . 1 k v c c 2 0 k v d d v d d 0 . 1 0 . 1 v c c 0 . 1 p s i g l c d p a n e l ( l c x 0 2 3 ) 1 0 0 . 1 1 0 1 c o m 3 1 s i g 1 3 s i g 3 5 s i g 5 7 s i g 7 9 s i g 9 1 1 s i g 1 1 1 3 s i d _ o u t c x a 2 1 1 1 r 6 v 3 3 8 r _ o u t 1 8 c l k h c x a 3 1 0 6 q 3 2 c l k l 3 1 g _ o u t 1 6 b _ o u t 1 4 d l y _ c n t 3 p o s _ c t r 1 1 p o s _ c t r 2 2 d i r _ c n t 4 o p e n o p e n o p e n o p e n s / h s / h s / h v c o m o f f s e t c a n c e l b u f f e r d c l o c k d e l a y s / h p u l s e s t i m i n g g e n e r a - t o r o f f s e t c a n c e l m o d e t i m i n g s i d i n v e r t a m p c a l i b r a - t i o n a m p 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 3 2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 6 4 6 3 6 2 6 1 6 0 5 9 5 8 5 7 5 6 5 5 5 4 5 3 5 2 5 1 5 0 4 9 c a l _ r c a l _ o c a l _ i v d d d g n d m c l k m c l k x g n d g n d d l y c t r c l k o u t c l k o u t x n c c l k i n c l k i n x f / h _ c n t p r g p o l n r g n c n c p o s c t r 1 p o s c t r 2 n c g n d g n d s t a t u s e n b d 1 o r 2 d i r c t r n c n c d c f b s w n c v i d e o _ i v i d e o _ r v i d e o _ o s h _ i n n c v c c g n d g n d s i d _ i n s i d _ r s i d _ o f r p s i g c n t v c o m o f f v c o m o u t s h o u t 1 n c s h o u t 2 n c s h o u t 3 n c p v c c g n d g n d p g n d n c s h o u t 4 n c s h o u t 5 n c s h o u t 6 v d d v d d v c c v d d v d d v d d 0 . 1 0 . 1 1 0 v d d v c c 5 v 1 5 . 5 v 0 . 1 1 0 s i g 1 2 1 4 s i g 1 0 1 2 s i g 8 1 0 s i g 6 8 s i g 4 6 s i g 2 4 s / h s / h s / h o f f s e t c a n c e l b u f f e r s / h s / h s / h o f f s e t c a n c e l b u f f e r s / h s / h s / h o f f s e t c a n c e l b u f f e r s / h s / h s / h o f f s e t c a n c e l b u f f e r s / h s / h s / h o f f s e t c a n c e l b u f f e r 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 f r p n r g e n b v d d 0 . 1 1 0 application circuits shown are typical examples illustrating the operation of the devices. sony cannot assume responsibility fo r any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same .
? 22 CXA3512R example of representative characteristics (v cc = 15.5v, v dd = 5.0v, sigcnt = 7.0v, ta = 25 3 c) c l k o u t p h a s e t o m c l k v s . d l y c t r v o l t a g e d l y c t r ( p i n 5 8 ) v o l t a g e [ v ] p h a s e [ d e g ] 4 4 . 5 3 1 8 0 1 2 0 6 0 0 6 0 1 2 0 1 8 0 3 . 5 5 s i d _ o v o l t a g e v s . s i d _ r v o l t a g e ( 1 ) s i d _ r ( p i n 3 8 ) v o l t a g e [ v ] s i d _ o ( p i n 3 7 ) v o l t a g e [ v ] 3 4 0 0 2 4 6 8 1 2 1 6 1 0 1 4 2 1 5 f r p = h i g h f r p = l o w s i d _ i n = 2 . 3 v s i d _ o v o l t a g e v s . s i d _ r v o l t a g e ( 2 ) s i d _ r ( p i n 3 8 ) v o l t a g e [ v ] s i d _ o ( p i n 3 7 ) v o l t a g e [ v ] 3 4 0 0 2 4 6 8 1 2 1 6 1 0 1 4 2 1 5 f r p = h i g h f r p = l o w s i d _ i n = 4 . 0 v s i d _ o v o l t a g e v s . s i d _ i n v o l t a g e ( 1 ) s i d _ i n ( p i n 3 9 ) v o l t a g e [ v ] s i d _ o ( p i n 3 7 ) v o l t a g e [ v ] 3 4 0 0 2 4 6 8 1 2 1 6 1 0 1 4 2 1 5 f r p = h i g h f r p = l o w s i d _ r = 3 . 3 v s i d _ o v o l t a g e v s . s i d _ i n v o l t a g e ( 2 ) s i d _ i n ( p i n 3 9 ) v o l t a g e [ v ] s i d _ o ( p i n 3 7 ) v o l t a g e [ v ] 3 4 0 0 2 4 6 8 1 2 1 6 1 0 1 4 2 1 5 f r p = h i g h f r p = l o w s i d _ r = 5 . 0 v d 1 o r 2 = h i g h m c l k = 2 0 m h z
? 23 CXA3512R v i d e o _ o v o l t a g e v s . v i d e o _ i n v o l t a g e ( 1 ) v i d e o _ i n ( p i n 4 7 ) v o l t a g e [ v ] v i d e o _ o ( p i n 4 5 ) v o l t a g e [ v ] 3 4 0 0 2 4 6 8 1 2 1 4 1 0 2 1 5 f r p = h i g h f r p = l o w v i d e o _ r = 3 . 3 v v i d e o _ o v o l t a g e v s . v i d e o _ r v o l t a g e ( 1 ) v i d e o _ r ( p i n 4 6 ) v o l t a g e [ v ] v i d e o _ o ( p i n 4 5 ) v o l t a g e [ v ] 2 3 4 0 2 4 6 8 1 0 1 2 1 5 f r p = h i g h f r p = l o w v i d e o _ i n = 1 . 8 v 5 v i d e o _ o v o l t a g e v s . v i d e o _ r v o l t a g e ( 2 ) v i d e o _ r ( p i n 4 6 ) v o l t a g e [ v ] v i d e o _ o ( p i n 4 5 ) v o l t a g e [ v ] 2 3 4 0 2 4 6 8 1 0 1 2 1 f r p = h i g h f r p = l o w v i d e o _ i n = 3 . 5 v v i d e o _ o v o l t a g e v s . v i d e o _ i n v o l t a g e ( 2 ) v i d e o _ i n ( p i n 4 7 ) v o l t a g e [ v ] v i d e o _ o ( p i n 4 5 ) v o l t a g e [ v ] 3 4 0 0 2 4 6 8 1 2 1 4 1 0 2 1 5 f r p = h i g h f r p = l o w v i d e o _ r = 5 . 0 v v c o m o u t v o l t a g e v s . v c o m o f f v o l t a g e v c o m o f f ( p i n 3 4 ) v o l t a g e [ v ] v c o m o u t ( p i n 3 3 ) v o l t a g e [ v ] 6 8 0 3 . 5 4 . 0 4 . 5 5 . 0 5 . 5 6 . 5 7 . 0 6 . 0 4 2 1 0
? 24 CXA3512R package outline unit: mm s o n y c o d e e i a j c o d e j e d e c c o d e p a c k a g e m a t e r i a l l e a d t r e a t m e n t l e a d m a t e r i a l p a c k a g e m a s s e p o x y r e s i n p a l l a d i u m p l a t i n g c o p p e r a l l o y p a c k a g e s t r u c t u r e l q f p - 6 4 p - l 0 2 l q f p 0 6 4 - p - 1 4 1 4 0 . 7 g 0 . 3 7 0 . 0 7 + 0 . 0 8 ( 0 . 3 5 ) ( 0 . 1 2 5 ) 0 . 1 4 5 0 . 0 4 6 4 p i n l q f p ( p l a s t i c ) 0 . 8 * 1 4 . 0 0 . 1 1 6 . 0 0 . 2 4 8 3 3 4 9 3 2 1 7 1 6 1 6 4 0 . 3 7 0 . 0 7 + 0 . 0 8 a b ( 0 . 5 ) ( 1 5 . 0 ) 1 . 7 m a x 0 . 1 0 . 1 3 m 0 . 1 0 . 1 0 . 2 5 ( 0 . 5 ) 0 . 6 0 . 2 0 t o 1 0 d e t a i l a d e t a i l b n o t e : d i m e n s i o n * d o e s n o t i n c l u d e m o l d p r o t r u s i o n . n o t e : p a l l a d i u m p l a t i n g t h i s p r o d u c t u s e s s - p d p p f ( s o n y s p e c . - p a l l a d i u m p r e - p l a t e d l e a d f r a m e ) .

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